Semiconductor devices generally use discrete devices such as metal oxide semiconductor (MOS) transistors as switching devices. As a semiconductor device becomes highly integrated, a MOS transistor may be scaled down. Thus, the channel length of the MOS transistor may decrease, resulting in a short channel effect. The decrease in the channel length may lead to a decrease in the width of a gate electrode, causing an increase in the electrical resistance of the gate electrode. To address the short channel effect problem, the junction depth of source/drain regions of the MOS transistor and the thickness of a gate insulating layer may both be reduced. As a result, the resistance (R) and the gate capacitance (C) of the gate electrode can increase. In this case, the transmission speed of an electric signal applied to the gate electrode may be delayed by a resistance-capacitance (RC) delay time.
In addition, since the source/drain regions have a shallow junction depth, their sheet resistance may increase. As a result, drivability of a single-channel MOS transistor may be reduced. For a high-performance MOS transistor suitable for a highly-integrated semiconductor device, a salicide (self-aligned silicide) process is widely used.
The salicide process is a processing technique for reducing the electrical resistance of a gate electrode and source/drain regions by selectively forming a metal silicide layer on the gate electrode and the source/drain regions. Recently, a salicide process in which a nickel silicide layer is formed using nickel has been used for manufacturing a high-performance MOS transistor. The nickel silicide layer can be formed at low temperature, its resistance does not increase with line narrowing, and a small amount of silicon is consumed.